A circuit original plate (which will be referred to as “reticle”, hereinafter) to be used for a lithography process includes a pattern arrangement region having a rectangular shape, and a mark arrangement region having a frame-like shape provided at the peripheral side of the pattern arrangement region. The pattern arrangement region is provided with a circuit pattern for forming a device pattern by light exposure. The mark arrangement region is provided with marks, such as an alignment mark and an overlay measurement mark. Along with the progress of scaling of semiconductor devices, circuit patterns have been downsized. However, the marks need to be optically monitored, and thus the size of the marks is set larger than that of the circuit pattern. Accordingly, there is a case where an overlay error between a mark and the circuit pattern is improper, because of an influence of the aberration of a lens for projecting the reticle in a reduced state.